1. Technical Field
The invention disclosed broadly relates to electrical testing and more particularly relates to testing complex logical devices.
2. Background Art
Prior art tester architectures, such as that shown in FIG. 1, employ a main processor 10 to exercise primary control over the test system and establish the test sequence and parameters according to an operational test program. Each pin, pin 1, pin 2, pin 3 . . . to pin N of a device under test 20 in FIG. 1, has its own corresponding pin electronics circuit including a decoder 16(1), 16(2), 16(3) to 16(N), and a driver/sensor 18(1), 18(2), 18(3), to 18(N), respectively. Where a device under test 20 has N pins, N pin electronic circuits, each including a decoder and a driver/sensor, are required, as is shown in FIG. 1.
A high speed local memory 14 has a data input connected to the main processor 10 and the bulk store 12 for receiving and storing a plurality of test vectors 15A to 15D, etc. Each test vector includes a plurality of N test words. For example, the test vector 15A includes the test words 15A(1), 15A(2), 15A(3), to 15A(N). A test vector can also include an instruction portion, for example the test vector 15A can include the instruction portion 15AI. During each testing cycle, the local memory 14 sequentially outputs the test words from a test vector. For example, the test word 15A(1) would be output to the decoder 16(1) and the test word 15A(2) would be output to the decoder 16(2), etc. for the vector 15A. The decoder 16(1) decodes the test word and applies a decoded output to the driver/sensor 18(1). Each driver/sensor 18(1) to 18(N) is controlled by its corresponding decoder 16(1) through 16(N) to provide any one of at least the following circuit functions: driver, detector, load, power supply, ground, open circuit, etc. The test function performed by a driver/sensor is determined by the test word output from the local memory 14 to the corresponding decoder connected to the driver/sensor. In response to the application of the testing function generated by a driver/sensor in FIG. 1, the corresponding pin of the device under test 20 will be subjected to an electrical manifestation or the absence of an electrical manifestation, in accordance with its function. For example, logical input pins of the device 20 will receive an electrical signal representing a binary one or a binary zero value as called for by the test program, power supply pins for the device under test will receive a voltage forcing or current forcing electrical value as called for by the test program, the load pins of the device 20 will be subjected to an appropriate electrical load as called for by the test program, the output pins will be conditioned to receive an output from the device under test 20 as directed by the test program, etc. Each driver/sensor 18(1) to 18(N), is connected by a feedback line 19 to the main processor 10 to indicate the pass/fail condition of the device under test 20, for analysis of any failures which may be detected.
Some prior art testers will include the provision for storing an instruction or a test pattern field 15AI for a test vector 15A in FIG. 1, to enable feeding back over line 17 information to the main processor 10 operating instructions for control of local memory 14 to enable data control such as branching, looping, etc.
A significant problem with prior art tester architecture such as that shown in FIG. 1 is the large memory size for the local memory 14 and the bulk store 12, which is required to accommodate the testing of a device under test 20 having a plurality N of pins greater than 100. With the advent of very large scale integrated circuits, the number of test cycles necessary to adequately test the highly complex logic on the device, coupled with the large number of pins for the device, creates a requirement for multi megabyte memory sizes for the local memory 14 in order to accommodate the test vectors.
One approach to solving this problem of large memory size requirements is the use of algorithmic pattern generators in the prior art. Algorithmic pattern generators of various types have been extensively used where test data is of a highly repetitive nature such as in memory testing. However, such pattern generators have a disadvantage of requiring high speed multiplexers in the signal paths or they require fixed (hardwired) connections to specific pins and are relatively expensive and inflexible and are not applicable to random logic.
Alternately, smaller tester memories can be used for storing fewer test vectors than are required for a complete test, and then the relatively small local memory can be sequentially loaded with test vectors for consecutive stages of testing. However, this reduces the overall throughput for testing since additional time is required to reload the local memory.